Technique for determining performance characteristics of electronic systems

ABSTRACT

A technique for determining performance characteristics of electronic systems is disclosed. In one exemplary embodiment, the technique may be realized as a method for determining performance characteristics of electronic systems. The method includes the steps of measuring a first response on a transmission medium from a falling edge transmitted on the transmission medium, and measuring a second response on the transmission medium from a rising edge transmitted on the transmission medium. The method also includes the step of determining worst case bit patterns for transmission on the transmission medium based upon the first response and the second response.

FIELD OF THE INVENTION

The present invention relates generally to integrated circuit testingtechniques and, more particularly, to a technique for determiningperformance characteristics of electronic systems.

BACKGROUND OF THE INVENTION

A typical transmission system comprises a transmitter, a receiver, andsome form of transmission medium for carrying a signal from thetransmitter to the receiver. A common problem that occurs in such atransmission system is that the signal arriving at the receiver may bedistorted by Inter-Symbol Interference (ISI), or some other form ofinterference inflicted upon the signal. That is, the waveform (timingand voltage) of the signal transmitted by the transmitter may differfrom the waveform of the signal received by the receiver. Mosttransmission systems are designed such that the system can accuratelyuse the received signal to decipher, or as a representation of, thetransmitted signal as long as the timing and voltage of the receivedsignal are within the timing and voltage margins of the system.

ISI generally occurs due to two mechanisms. First, the timing or voltageof a signal presently being transmitted on any given transmission mediummay be affected by residual reflections from prior transmitted signalson the same transmission medium. Second, adjacent transmission media mayhave electromagnetic coupling. In such a case, the timing or voltage ofsignals transmitted on a given transmission medium may be influenced bysignals transmitted on other adjacent transmission mediums.

When testing transmission systems, the operation of such systems isoften measured by transmitting long sequences of random data. To somedegree, the accuracy of this approach depends upon the probability ofthe random data sequences containing a worst case data pattern (i.e.,the data pattern resulting in the greatest amount of distortion to areceived signal). The accuracy of this approach is also dependent uponwhether there is ISI or some other form of interference associated withthe device or system. Further, the measurement apparatus may exhibit ISIor some other form of interference, thereby introducing an additionaluncertainty. In some cases, guard-banding is employed to deal with theseuncertainties.

Referring to FIG. 1, there is shown a typical apparatus 10 for testingthe operation of an integrated circuit (IC) memory device 12. Theapparatus 10 comprises a vector memory 14 for storing random datasequences. The vector memory 14 is connected to a transmitter 16 fortransmitting the random data sequences along a transmission medium 18 tothe IC memory device 12. The apparatus 10 also comprises a receiver 20for receiving data transmitted from the IC memory device 12 via thetransmission medium 18, and a result memory 22, connected to thereceiver 20, for storing the received data. The operation of the ICmemory device 12 is tested by comparing the random data sequences thatare transmitted from the vector memory 14 to the IC memory device 12 forstorage therein with the same random data sequences after they aretransmitted from the IC memory device 12 to the result memory 22 forstorage therein. It should be noted that although only one transmitter16, transmission medium 18, and receiver 20 are shown, this arrangementmay be duplicated as required based upon the number of input/output(I/O) lines of the IC memory device 12 to be measured.

The apparatus 10 can also be used to attempt to measure the worst casetiming and voltage margins of the IC memory device 12 by measuring theoutput waveforms of the random data sequences after they are transmittedfrom the IC memory device 12 to the result memory 22. However, sincethere is no way to know when a worst case data pattern will occur, everyoutput waveform must be measured. Also, this method is not guaranteed tofind the worst case timing and voltage margins since the random datasequences may not include the worst case data pattern. This isespecially true when the outputs of the IC memory device 12 are affectedby ISI or some other form of interference. In addition, if the apparatus10 itself has ISI or some other form of interference, the measurementresult will not accurately reflect the true worst case timing andvoltage margins of the IC memory device 12.

In view of the foregoing, it would be desirable to provide a techniquefor determining performance characteristics of electronic systems whichovercomes the above-described inadequacies and shortcomings.

SUMMARY OF THE INVENTION

According to the present invention, a technique for determiningperformance characteristics of electronic systems is provided. In oneexemplary embodiment, the technique may be realized as a method fordetermining performance characteristics of electronic systems. Themethod includes the steps of measuring a first response on atransmission medium from a falling edge transmitted on the transmissionmedium, and measuring a second response on the transmission medium froma rising edge transmitted on the transmission medium. The method alsoincludes the step of determining worst case bit patterns fortransmission on the transmission medium based upon the first responseand the second response.

In accordance with other aspects of this particular exemplary embodimentof the present invention, the method may also beneficially include thestep of transmitting the worst case bit patterns from an electronicdevice onto the transmission medium for determining performancecharacteristics associated with the electronic device and thetransmission medium. The performance characteristics may beneficiallyinclude worst case timing margins and/or worst case voltage marginsassociated with the electronic device and the transmission medium.

In accordance with further aspects of this particular exemplaryembodiment of the present invention, the step of measuring a firstresponse on a transmission medium may beneficially include the steps ofsampling the voltage of the first response on the transmission medium,calculating the difference between each voltage sample and a steadystate reference voltage, and generating a falling edge vector based uponthe differences between each voltage sample and the steady statereference voltage. The voltage of the first response on the transmissionmedium may be periodically or non-periodically sampled.

In accordance with still further aspects of this particular exemplaryembodiment of the present invention, the step of measuring a secondresponse on a transmission medium may beneficially include the steps ofsampling the voltage of the second response on the transmission medium,calculating the difference between each voltage sample and a steadystate reference voltage, and generating a rising edge vector based uponthe differences between each voltage sample and the steady statereference voltage. The voltage of the second response on thetransmission medium may be periodically or non-periodically sampled.

In accordance with additional aspects of this particular exemplaryembodiment of the present invention, the step of determining worst casebit patterns may beneficially include determining worst case timingmargin bit patterns and/or worst case voltage margin bit patterns fortransmission on the transmission medium. For example, the step ofdetermining worst case bit patterns may beneficially include the step ofchoosing a type of signal degradation parameter from a low side signaldegradation, a high side signal degradation, a signal edge pull-in, or asignal edge push-off. The step of determining worst case bit patternsmay also beneficially include the step of choosing an ending conditionfrom a low output voltage level or a high output voltage level. The stepof determining worst case bit patterns may also beneficially include thestep of analyzing a falling edge vector generated based upon the firstresponse or a rising edge vector generated based upon the secondresponse to determine whether or not a state transition will cause adesired signal degradation at the ending condition. The step ofdetermining worst case bit patterns may also beneficially include thestep of analyzing the falling edge vector or the rising edge vector todetermine whether or not a state transition will cause a desired signaldegradation at each previously occurring bit time. This last step isbeneficially repeated using a desired amount of the falling edge vectorand the rising edge vector.

In an alternative exemplary embodiment, the technique may be realized asan integrated circuit device having a transmitter for transmittingsignals from the integrated circuit device onto a transmission medium.The integrated circuit device comprises a falling edge generatorelectrically connected to the transmitter for generating a falling edgesignal for transmission by the transmitter onto the transmission mediumso as to provide a falling edge response associated with thetransmission medium for generating an associated falling edge vector.The integrated circuit device also comprises a rising edge generatorelectrically connected to the transmitter for generating a rising edgesignal for transmission by the transmitter onto the transmission mediumso as to provide a rising edge response associated with the transmissionmedium for generating an associated rising edge vector. In accordancewith this particular exemplary embodiment of the present invention, thefalling edge generator and the rising edge generator may be formed in acombined falling/rising edge generator.

In another alternative exemplary embodiment, the technique may berealized as an integrated circuit device having a receiver for receivingsignals from a transmission medium. The integrated circuit devicecomprises a sampling and differencing circuit electrically connected tothe transmission medium for sampling a signal propagating along thetransmission medium prior to being received by the receiver, and forcalculating the difference between a sampled signal value and areference value.

The present invention will now be described in more detail withreference to exemplary embodiments thereof as shown in the appendeddrawings. While the present invention is described below with referenceto preferred embodiments, it should be understood that the presentinvention is not limited thereto. Those of ordinary skill in the arthaving access to the teachings herein will recognize additionalimplementations, modifications, and embodiments, as well as other fieldsof use, which are within the scope of the present invention as disclosedand claimed herein, and with respect to which the present inventioncould be of significant utility.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to facilitate a fuller understanding of the present invention,reference is now made to the appended drawings. These drawings shouldnot be construed as limiting the present invention, but are intended tobe exemplary only.

FIG. 1 shows a typical prior art apparatus for testing the operation ofan integrated circuit (IC) memory device.

FIG. 2 shows a graph indicating a typical output voltage waveform rangefor a logic one pulse and a typical output voltage waveform range for alogic zero pulse for an integrated circuit (IC) device.

FIG. 3 shows a graph indicating a logic one pulse having rising andfalling edges that fall outside the output voltage waveform range ofFIG. 2, and a logic zero pulse having rising and falling edges that falloutside the output voltage waveform range of FIG. 2.

FIG. 4 shows a graph indicating a logic one pulse having a voltage levelthat falls outside the output voltage waveform range of FIG. 2, and alogic zero pulse having a voltage level that falls outside the outputvoltage waveform range of FIG. 2.

FIG. 5 shows a graph indicating a typical falling edge output voltagewaveform for an IC device that is periodically sampled until a steadystate output voltage level is reached in accordance with an embodimentof the present invention.

FIG. 6 shows a graph indicating a typical rising edge output voltagewaveform for an IC device that is periodically sampled until a steadystate output voltage level is reached in accordance with an embodimentof the present invention.

FIG. 7 shows a sampling and differencing circuit for periodicallysampling the output voltage from an IC device, and for calculating thedifference between the sampled output voltage and a steady statereference voltage, in accordance with an embodiment of the presentinvention.

FIG. 8 shows an example of an output voltage response for an IC devicefor a last bit transition of low-to-high that is periodically sampleduntil a steady state output voltage level is reached in accordance withthe present invention.

FIG. 9 shows an example of an output voltage response for an IC devicefor a last bit transition of high-to-low that is periodically sampleduntil a steady state output voltage level is reached in accordance withthe present invention.

FIG. 10 shows an embodiment of the present invention wherein afalling/rising edge generator is beneficially connected to a transmitterof a transmission system, and a sampling and differencing circuit isbeneficially connected to a receiver of the transmission system, suchthat the worst case performance characteristics of the entiretransmission system can be determined.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENT(S)

By way of introduction to the present invention, FIG. 2 shows a graphindicating a typical output voltage waveform range 30 for a logic onepulse and a typical output voltage waveform range 32 for a logic zeropulse for an integrated circuit (IC) device (not shown). These outputvoltage waveform ranges 30 and 32 apply to the IC device as it operateswithin a particular system. That is, depending upon system operatingconditions, these output voltage waveform ranges 30 and 32 may vary. Forthis reason, the output voltage waveform ranges 30 and 32 are typicallyindustry standards, which are established assuming a defined set ofsystem operating conditions. This is done to insure that similar ICdevices operate in a similar manner under similar system operatingconditions.

Unfortunately, the defined set of system operating conditions is notall-inclusive. That is, the defined set of system operating conditionsdoes not include several operating conditions that are typically presentin any particular system. For example, ISI, humidity, and other systemoperating conditions may adversely affect the operation of the ICdevice. That is, the IC device will typically provide a logic one pulsesuch that it falls within the output voltage waveform range 30, and alogic zero pulse such that it falls within the output voltage waveformrange 32. However, depending upon these other system operatingconditions, the IC device may provide a logic one pulse that fallsoutside the output voltage waveform range 30, and a logic zero pulsethat falls outside the output voltage waveform range 32. If thishappens, an error may occur if the logic one pulse is not properlydetected as a logic one pulse, or the logic zero pulse is not properlydetected as a logic zero pulse. Referring to FIG. 3, there is shown acondition wherein the IC device provides a logic one pulse 34 havingrising and falling edges that fall outside the output voltage waveformrange 30. Similarly, FIG. 3 also shows a condition wherein the IC deviceprovides a logic zero pulse 36 having rising and falling edges that falloutside the output voltage waveform range 32. Also, referring to FIG. 4,there is shown a condition wherein the IC device provides a logic onepulse 38 having a voltage level (i.e., V_(oh) level) that falls outsidethe output voltage waveform range 30. Similarly, FIG. 4 also shows acondition wherein the IC device provides a logic zero pulse 40 having avoltage level (i.e., V_(ol)) that falls outside the output voltagewaveform range 32.

The operating conditions that cause an IC device to provide outputsignals that fall outside the typical output voltage waveform ranges(i.e., outside output voltage waveform ranges 30 and 32) are commonlycalled the worst case operating conditions. These worst case operatingconditions may result from ISI, humidity, and other deleterious affects.In any event, it is important to know how an IC device operates underthese worst case operating conditions, and when these worst caseoperating conditions occur for each particular IC device. The followingdescription sets forth a methodology for determining a worst case bitpattern for an IC device, and for determining a worst case outputvoltage response associated with that worst case bit pattern.

Referring to FIG. 5, there is shown a graph indicating a typical fallingedge output voltage waveform 42 for an IC device (not shown). Thefalling edge output voltage waveform 42 is periodically (oralternatively non-periodically) sampled until a steady state outputvoltage level 44 is reached. The steady state output voltage level 44may be defined by several standards such as, for example, when theoutput voltage level has a swing that does not vary by more than 0.5%.

At each sampling point (Cfx), the difference (Dfx) between the sampledvoltage level and the steady state voltage level 44 is calculated. Afalling edge vector is then generated based upon these differences (Dfx)in voltage level values. For example, the falling edge vector,

-   -   F=(Df1, Df2, Df3, Df4, Df5, Df6, . . . , Dfn)        is generated, wherein Dfx=Cfx−steady state voltage level 44.

Similarly, referring to FIG. 6, there is shown a graph indicating atypical rising edge output voltage waveform 46 for the IC device (notshown). The rising edge output voltage waveform 46 is periodically (oralternatively non-periodically) sampled until a steady state outputvoltage level 48 is reached. The steady state output voltage level 48may be defined by several standards such as, for example, when theoutput voltage level has a swing that does not vary by more than 0.5%.

At each sampling point (Crx), the difference (Drx) between the sampledvoltage level and the steady state voltage level 48 is calculated. Arising edge vector is then generated based upon these differences (Drx)in voltage level values. For example, the rising edge vector,

-   -   R=(Dr1, Dr2, Dr3, Dr4, Dr5, Dr6, . . . , Drn)        is generated, wherein Drx=Crx−steady state voltage level 48.

Referring to FIG. 7, there is shown a sampling and differencing circuit50 for periodically (or alternatively non-periodically) sampling anoutput voltage signal from the IC device, and for calculating thedifference between the sampled output voltage and a steady statereference voltage. The sampling and differencing circuit 50 comprises acomparator 52, a trigger circuit 54, a reference voltage circuit 56, anoptional tunable delay circuit 58, and an optional variable loss pathcircuit 60. The output voltage signal from the IC device (either afalling edge signal 42 or a rising edge signal 46) is provided to thecomparator 52. This output voltage signal from the IC device is comparedagainst a reference voltage (e.g., Vol for a falling edge, Voh for arising edge) provided by the reference voltage circuit 56. Thiscomparison is periodically (or alternatively non-periodically) conductedbased upon the frequency or other triggering measure of the triggercircuit 54. The comparator 52 outputs a difference signal, D, for use ingenerating a falling or rising edge vector, F or R, respectively. Itshould be noted that the level of the reference voltage is typicallyupdated based upon feedback received from the output of the comparator52.

The frequency or other triggering measure of the comparison may bevaried using, for example, the optional tunable delay circuit 58. Also,the reference voltage may be varied using, for example, the optionalvariable loss path circuit 60, or other means to allow for betterresolution of AC signal levels at sampling times. Further, the samplingand differencing circuit 50 could be replaced with an analog-to-digitalconverter, or some other circuitry that is functionally equivalent tothe sampling and differencing circuit 50.

At this point is should be noted that, although voltage is sampled andused above to generate the falling and rising edge vectors, F and R,respectively, other signaling metrics may be used in accordance with thepresent invention. For example, the signaling metric could be sampledcurrent or energy output from the IC device, or a weighted function overtime. The weighted function over time could include hardware specificeffects, and could use different measures than exact voltages todetermine the effects.

Using the falling and rising edge vectors, F and R, respectively, theoutput voltage response from an arbitrary bit pattern may be predictedor approximated for the IC device. For example, the output voltageresponse, V(t), for bit pattern 10001000 (reading left to right from bit0 to bit 7) may be predicted or approximated as follows:

At time t0, the output voltage response is equal to the value of bit 0(i.e., Voh). Thus, V(t0)=Voh.

At time t1, since a state transition occurs, the output voltage responseis equal to the value of bit 0 (i.e., Voh) minus Δ plus Df1 (whereinΔ=Voh−Vol, which represents a state change in the bit pattern). Thus,V(t1)=Voh−Δ+Df1.

At time t2, since no state transition occurs, the output voltageresponse is equal to the value of bit 0 (i.e., Voh) minus Δ plus Df2.Thus, V(t2)=Voh−Δ+Df2.

At time t3, since no state transition occurs, the output voltageresponse is equal to the value of bit 0 (i.e., Voh) minus Δ plus Df3.Thus, V(t3)=Voh−Δ+Df3.

At time t4, since a state transition occurs, the output voltage responseis equal to the value of bit 0 (i.e., Voh) minus Δ plus Δ plus Df4 plusDr1. Thus, V(t4)=Voh−Δ+Δ+Df4+Dr1.

At time t5, since a state transition occurs, the output voltage responseis equal to the value of bit 0 (i.e., Voh) minus Δ plus Δ minus Δ plusDf5 plus Dr2 plus Df1. Thus, V(t5)=Voh−Δ+Δ−Δ+Df5+Dr2+Df1.

At time t6, since no state transition occurs, the output voltageresponse is equal to the value of bit 0 (i.e., Voh) minus Δ plus Δ minusΔ plus Df6 plus Dr3 plus Df2. Thus, V(t6)=Voh−Δ+Δ−Δ+Df6+Dr3+Df2.

At time t7, since no state transition occurs, the output voltageresponse is equal to the value of bit 0 (i.e., Voh) minus Δ plus Δ minusΔ plus Df7 plus Dr4 plus Df3. Thus, V(t7)=Voh−Δ+Δ−Δ+Df7+Dr4+Df3.

The above pattern continues until all of the falling and rising edgevector values are used, at which point only a steady state outputvoltage response remains. Thus, the overall output voltage response,V(t), may be defined asV(t0)+V(t1)+V(t2)+V(t3)+V(t4)+V(t5)+V(t60)+V(t7)+. . . .

Using the falling and rising edge vectors, F and R, respectively, theworst case bit pattern for the IC device can be determined, as well asthe worst case output voltage response associated with that worst casebit pattern. Of course, there may be eight different worst case bitpatterns for the IC device depending upon the type of signal degradationparameter (i.e., low side signal degradation, high side signaldegradation, signal edge pull-in, or signal edge push-off) and the typeof ending condition (i.e., Vol or Voh) that is of interest. That is, lowside signal degradation occurs when the output voltage response for alogic zero state rises above Vol, high side signal degradation occurswhen the output voltage response for a logic one state drops below Voh,signal edge pull-in occurs when the output voltage response for a logicstate transition occurs early, and signal edge push-off occurs when theoutput voltage response for a logic state transition occurs late. Also,a Vol ending condition occurs when a logic zero state should be present,and a Voh ending condition occurs when a logic one state should bepresent. Accordingly, there may be eight different worst case bitpatterns for the IC device, and each of these eight worst case bitpatterns for the IC device may be determined using the falling andrising edge vectors, F and R, respectively.

The method for determining any of the worst case bit patterns for the ICdevice begins by first choosing the type of signal degradation parameter(i.e., low side signal degradation, high side signal degradation, signaledge pull-in, or signal edge push-off). An ending condition must then bechosen (i.e., either Vol or Voh). Next, the falling and rising edgevectors, F and R, respectively, must be analyzed to determine whether ornot a state transition will cause a desired signal degradation at theending condition. Next, the falling and rising edge vectors, F and R,respectively, must be analyzed to determine whether or not a statetransition will cause a desired signal degradation at each previouslyoccurring bit time. This last step is repeated until a desired amount ofthe falling and rising edge vectors, F and R, respectively, are used. Aworst case pattern will result for the chosen type of signal degradationparameter and ending condition.

By way of a first example, assume the following values for the fallingand rising edge vectors, F and R, respectively:

-   -   F=(0, 0.1, 0.1, −0.1, 0.05)    -   R=(0.1, 0, −0.1, 0.05, 0.05)

Using the above falling and rising edge vectors, F and R, respectively,assume that the worst case bit pattern for low side signal degradationis desired. Also, assume an ending condition of Vol has been chosen. Thegoal of low side signal degradation is to maximize the positive ACeffects on the low side of the output voltage response. For each bittime, the worst case bit pattern is determined as follows:

Bit 4: Since the ending condition of Vol (at bit 5) has been chosen, thelogic level of bit 4 must be determined based upon the effects of afalling edge or no edge, which are the only possibilities that may beused to arrive at the ending condition of Vol (at bit 5). Since Df1=0, afalling edge does not cause any positive low side signal degradation atbit 5. Thus, bit 4 should have a logic level of Vol.

Bit 3: Since bit 4 is at Vol, the logic level of bit 3 must bedetermined based upon the effects of a falling edge or no edge, whichare the only possibilities that may be used to arrive at the logic levelof Vol at bit 4. Since Df2=0.1, a falling edge causes positive low sidesignal degradation at bit 4. Thus, bit 3 should have a logic level ofVoh.

Bit 2: Since bit 3 is at Voh, the logic level of bit 2 must bedetermined based upon the effects of a rising edge or no edge, which arethe only possibilities that may be used to arrive at a logic level ofVoh at bit 3. Since Dr3=−0.1, a rising edge does not cause any positivelow side signal degradation at bit 3. Thus, bit 2 should have a logiclevel of Voh.

Bit 1: Since bit 2 is at Voh, the logic level of bit 1 must bedetermined based upon the effects of a rising edge or no edge, which arethe only possibilities that may be used to arrive at a logic level ofVoh at bit 2. Since Dr4=0.05, a rising edge causes positive low sidesignal degradation at bit 2. Thus, bit 1 should have a logic level ofVol.

Bit 0: Since bit 1 is at Vol, the logic level of bit 0 must bedetermined based upon the effects of a falling edge or no edge, whichare the only possibilities that may be used to arrive at a logic levelof Vol at bit 1. Since Df5=0.05, a falling edge causes positive low sidesignal degradation at bit 1. Thus, bit 0 should have a logic level ofVoh.

In view of the foregoing, the worst case bit pattern for low side signaldegradation and an ending condition of Vol for the IC device is 101100(reading left to right from bit 0 to bit 5). This worst case bit patterncauses low side signal degradation at bit 5 in the amount ofVol+0.2=Vol+0+0.1+0+0.05+0.05=Vol+0+Df2+0+Dr4+Df5. Of course, this worstcase bit pattern and the resulting low side signal degradation at bit 5is based upon the above-defined falling and rising edge vectors, F andR, respectively.

By way of a second example, assume the same values for the falling andrising edge vectors, F and R, respectively, as defined above. Using theabove-defined falling and rising edge vectors, F and R, respectively,assume that the worst case bit pattern for high side signal degradationis desired. Also, assume an ending condition of Voh has been chosen. Thegoal of high side signal degradation is to maximize the negative ACeffects on the high side of the output voltage response. For each bittime, the worst case bit pattern is determined as follows:

Bit 4: Since the ending condition of Voh (at bit 5) has been chosen, thelogic level of bit 4 must be determined based upon the effects of arising edge or no edge, which are the only possibilities that may beused to arrive at the ending condition of Voh (at bit 5). Since Dr1=0.1,a rising edge does not cause any negative high side signal degradationat bit 5. Thus, bit 4 should have a logic level of Voh.

Bit 3: Since bit 4 is at Voh, the logic level of bit 3 must bedetermined based upon the effects of a rising edge or no edge, which arethe only possibilities that may be used to arrive at the logic level ofVoh at bit 4. Since Dr2=0, a rising edge does not cause any negativehigh side signal degradation at bit 4. Thus, bit 3 should have a logiclevel of Voh.

Bit 2: Since bit 3 is at Voh, the logic level of bit 2 must bedetermined based upon the effects of a rising edge or no edge, which arethe only possibilities that may be used to arrive at a logic level ofVoh at bit 3. Since Dr3=−0.1, a rising edge causes negative high sidesignal degradation at bit 3. Thus, bit 2 should have a logic level ofVol.

Bit 1: Since bit 2 is at Vol, the logic level of bit 1 must bedetermined based upon the effects of a falling edge or no edge, whichare the only possibilities that may be used to arrive at a logic levelof Vol at bit 2. Since Df4=−0.1, a falling edge causes negative highside signal degradation at bit 2. Thus, bit 1 should have a logic levelof Voh.

Bit 0: Since bit 1 is at Voh, the logic level of bit 0 must bedetermined based upon the effects of a rising edge or no edge, which arethe only possibilities that may be used to arrive at a logic level ofVoh at bit 1. Since Dr5=0.05, a rising edge does not cause any negativehigh side signal degradation at bit 1. Thus, bit 0 should have a logiclevel of Voh.

In view of the foregoing, the worst case bit pattern for high sidesignal degradation and an ending condition of Voh for the IC device is110111 (reading left to right from bit 0 to bit 5). This worst case bitpattern causes high side signal degradation at bit 5 in the amount ofVoh−0.2=Voh−0−0−0.1−0.1−0=Voh−0−0−Dr3−Df4−0. Of course, this worst casebit pattern and the resulting high side signal degradation at bit 5 isbased upon the above-defined falling and rising edge vectors, F and R,respectively.

The worst case bit pattern for low side signal degradation and an endingcondition of Voh and the worst case bit pattern for high side signaldegradation and an ending condition of Vol are determined in a mannersimilar to the first and second examples set forth above.

The worst case bit patterns for signal edge pull-in and signal edgepush-off and ending conditions of Vol and Voh are also determined in amanner similar to the first and second examples set forth above. Theworst case bit patterns for signal edge pull-in and signal edge push-offcan be determined using the same falling and rising edge vectors, F andR, respectively, that are used to determine the worst case bit patternsfor low side signal degradation and high side signal degradation.However, for signal edge pull-in and signal edge push-off, it ispreferred to have the voltage waveforms sampled closer to the rising andfalling edges.

For signal edge pull-in and signal edge push-off, an assumption must bemade about the last bit transition (i.e., high-to-low or low-to-high).Referring to FIG. 8, there is shown an example of an output voltageresponse 80 for the IC device for a last bit transition of low-to-high.For signal edge push-off, the voltage in range A of FIG. 8 should belowered. For signal edge pull-in, the voltage in range A of FIG. 8should be raised. Referring to FIG. 9, there is shown an example of anoutput voltage response 90 for the IC device for a last bit transitionof high-to-low. For signal edge push-off, the voltage in range A of FIG.9 should be raised. For signal edge pull-in, the voltage in range A ofFIG. 9 should be lowered.

One way to achieve signal edge push-off or signal edge pull-in withinrange A in FIGS. 8 and 9 is to target a point such as point B in FIGS. 8and 9. To determine how a bit pattern impacts point B in FIGS. 8 and 9,the rising edge waveform of FIG. 8 and the falling edge waveform of FIG.9 are each sampled to determine the voltage values at periodic (oralternatively non-periodic) intervals from point B in FIGS. 8 and 9.These sampled voltage values are then used to generate rising andfalling edge vectors, similar to the above-described rising and fallingedge vectors, R and F. respectively. These generated rising and fallingedge vectors can then be used in a manner similar to the above-describedrising and falling edge vectors, R and F, respectively, to determine anincrease or decrease in the voltage level at point B in FIGS. 8 and 9.Thus, these generated rising and falling edge vectors can be used todetermine the worst case push-off/pull-in bit patterns for the ICdevice, as well as the worst case output voltage response associatedwith those worst case bit patterns. These generated rising and fallingedge vectors can also be used to predict or approximate the outputvoltage response of the IC device for an arbitrary bit pattern.

Once the worst case bit patterns for the IC device are determined, theperformance characteristics of the IC device can then also bedetermined. For example, the worst case bit patterns may be transmittedfrom an electronic device onto a transmission medium for determiningperformance characteristics associated with the electronic device andthe transmission medium. The performance characteristics may include,for example, worst case timing margins and/or worst case voltage marginsassociated with the electronic device and the transmission medium.

Referring to FIG. 10, there is shown an embodiment of the presentinvention wherein a transmission system 100 comprises a source 102(e.g., a first IC device) and a destination 104 (e.g., a second ICdevice). The source 102 includes a transmitter 106 for transmitting asignal, S, on a corresponding transmission medium 108. The source 102also includes a falling/rising edge generator 112 for generating afalling edge or a rising edge for use in generating the above-describedrising and falling edge vectors, R and F, respectively. Of course, thefalling/rising edge generator 112 could be formed as a separate fallingedge generator and a separate rising edge generator.

The destination 104 includes a receiver 110 for receiving the signaltransmitted on the transmission medium 108, and outputting a receivedsignal, S′. The destination 104 also includes the sampling anddifferencing circuit 50 shown in FIG. 7 for periodically (oralternatively non-periodically) sampling the output voltage from thetransmitter 106, and for calculating the difference between the sampledoutput voltage and a steady state reference voltage. Of course, aspreviously described, the sampling and differencing circuit 50 could bereplaced by an analog-to-digital converter, or some other circuitry thatmay be used to generate the falling and rising edge vectors, F and R,respectively.

At this point it should be noted that, while only a single transmitter106, transmission medium 108, receiver 110, falling/rising edgegenerator 112, and sampling and differencing circuit 50 are shown inFIG. 10, this arrangement of components in the transmission system 100may be duplicated as required. For example, the source 102 may include aplurality of transmitters 106, the destination 104 may include arespective plurality of receivers 110, and a respective plurality oftransmission mediums 108 may connect the plurality of transmitters 106and the plurality of receivers 110, as is typical in many transmissionsystems. Each of the plurality of transmitters 106 could then have anassociated falling/rising edge generator 112, and each of the pluralityof receivers 110 could then have an associated sampling and differencingcircuit 50.

The transmission system 100, and specifically the falling/rising edgegenerator 112 and the sampling and differencing circuit 50, operate suchthat the worst case performance characteristics of the entiretransmission system 100 can be determined in accordance with the presentinvention as described in detail above.

The above-described technique may be summarized in mathematical terms.That is, the above-described technique includes an attempt to representan arbitrary function (i.e., output waveform) by a linear combination ofsome basis functions (i.e., rising- and falling-edge responses). Forexample, the voltage response, V(t), may be expressed as:V(t)=sum(a _(n) R(t+n*t 0)+b _(n) F(t+n*t 0))wherein 0≦n<N of interest, and t0 is a bit time.

For a target V(t) (of worst case high/low voltage or pull-in/push-outdelay), the coefficients (i.e., bit sequence) of a_(n) and b_(n) can bedetermined in more than one way. That is, while the above-describedtechnique is a (preferred) systematic approach of finding a_(n) andb_(n), a brute-force approach may also be used to select the one ofinterest among all combinations of a_(n) and b_(n). It is believed thatthe former may be more efficient to implement in software, while thelatter may be easier to implement in hardware.

Assume that R corresponds to a rising-edge response when starting from aDC steady state of Vol, while F corresponds to a falling-edge responsewhen starting from a DC steady state of Voh. For a linear circuit, R andF form a complete set of basis functions. For nonlinear circuits, morefunctions may be brought in to form a complete set (because ripples canaffect the response). For example, R1, R2, . . . , and F1, F2, . . . ,can be used where R1 corresponds to a rising-edge response if there is afalling edge 1 bit time before, R2 corresponds to a rising-edge responseif there is a falling edge 2 bit time before, etc., and F1 correspondsto a falling-edge response if there is a rising edge 1 bit time before,F2 corresponds to a falling-edge response if there is a rising edge 2bit time before, etc.

To obtain R1, R2, . . . , and F1, F2, . . . , a single-bit, 2-bit, . . ., response needs to be recorded. Of course, if only R and F are used, itwill still be a very good 1st-order approximation in nonlinear circuits.

At this point it should be noted that determining the worst caseperformance characteristics of an IC device or an entire transmissionsystem in accordance with the present invention as described abovetypically involves the processing of input data and the generation ofoutput data to some extent. This input data processing and output datageneration may be implemented in hardware or software. For example,specific electronic components may be employed in a transmission systemor in a testing apparatus for implementing the functions associated withdetermining the worst case performance characteristics of an IC deviceor the entire transmission system in accordance with the presentinvention as described above. Alternatively, a processor operating inaccordance with stored instructions may implement the functionsassociated with determining the worst case performance characteristicsof an IC device or an entire transmission system in accordance with thepresent invention as described above. If such is the case, it is withinthe scope of the present invention that such instructions may betransmitted to an IC device, a transmission system, or a testingapparatus via one or more signals.

The present invention apparatus and method described herein suffer fromnone of the drawbacks associated with prior art as described above sincethe worst case performance is calculated based upon waveforms producedby only a single rising edge and a single falling edge. Also, inaccordance with the present invention, a measurement instrument can bemeasured in advance and an inverse transfer function can be applied tonull-out ISI or any other form of interference inherent in themeasurement instrument. The present invention is not to be limited inscope by the specific embodiments described herein. Indeed, variousmodifications of the present invention, in addition to those describedherein, will be apparent to those of ordinary skill in the art from theforegoing description and accompanying drawings. Thus, suchmodifications are intended to fall within the scope of the followingappended claims. Further, although the present invention has beendescribed herein in the context of a particular implementation in aparticular environment for a particular purpose, those of ordinary skillin the art will recognize that its usefulness is not limited thereto andthat the present invention can be beneficially implemented in any numberof environments for any number of purposes. Accordingly, the claims setforth below should be construed in view of the full breath and spirit ofthe present invention as disclosed herein.

1. A method for determining performance characteristics of electronicsystems, the method comprising the steps of: measuring a first responseon a transmission medium from a falling edge transmitted on thetransmission medium; measuring a second response on the transmissionmedium from a rising edge transmitted on the transmission medium; anddetermining worst case bit patterns for transmission on the transmissionmedium based upon the first response and the second response.
 2. Themethod as defined in claim 1, further comprising the step of:transmitting the worst case bit patterns from an electronic device ontothe transmission medium for determining performance characteristicsassociated with the electronic device and the transmission medium. 3.The method as defined in claim 2, wherein the performancecharacteristics include worst case timing margins associated with theelectronic device and the transmission medium.
 4. The method as definedin claim 2, wherein the performance characteristics include worst casevoltage margins associated with the electronic device and thetransmission medium.
 5. The method as defined in claim 2, wherein theperformance characteristics include worst case timing and voltagemargins associated with the electronic device and the transmissionmedium.
 6. The method as defined in claim 1, wherein the step ofmeasuring a first response on a transmission medium includes the stepof: sampling the voltage of the first response on the transmissionmedium.
 7. The method as defined in claim 6, wherein the step ofsampling the voltage of the first response on the transmission mediumincludes periodically sampling the voltage of the first response on thetransmission medium.
 8. The method as defined in claim 6, wherein thestep of sampling the voltage of the first response on the transmissionmedium includes non-periodically sampling the voltage of the firstresponse on the transmission medium.
 9. The method as defined in claim6, wherein the step of measuring a first response on a transmissionmedium also includes the step of: calculating the difference betweeneach voltage sample and a steady state reference voltage.
 10. The methodas defined in claim 9, wherein the step of measuring a first response ona transmission medium also includes the step of: generating a fallingedge vector based upon the differences between each voltage sample andthe steady state reference voltage.
 11. The method as defined in claim1, wherein the step of measuring a second response on the transmissionmedium includes the step of: sampling the voltage of the second responseon the transmission medium.
 12. The method as defined in claim 11,wherein the step of sampling the voltage of the second response on thetransmission medium includes periodically sampling the voltage of thesecond response on the transmission medium.
 13. The method as defined inclaim 11, wherein the step of sampling the voltage of the secondresponse on the transmission medium includes non-periodically samplingthe voltage of the second response on the transmission medium.
 14. Themethod as defined in claim 11, wherein the step of measuring a secondresponse on the transmission medium also includes the step of:calculating the difference between each voltage sample and a steadystate reference voltage.
 15. The method as defined in claim 14, whereinthe step of measuring a second response on the transmission medium alsoincludes the step of: generating a rising edge vector based upon thedifferences between each voltage sample and the steady state referencevoltage.
 16. The method as defined in claim 1, wherein the step ofdetermining worst case bit patterns includes determining worst casetiming margin bit patterns for transmission on the transmission medium.17. The method as defined in claim 1, wherein the step of determiningworst case bit patterns includes determining worst case voltage marginbit patterns for transmission on the transmission medium.
 18. The methodas defined in claim 1, wherein the step of determining worst case bitpatterns includes determining worst case timing margin bit patterns andworst case voltage margin bit patterns for transmission on thetransmission medium.
 19. The method as defined in claim 1, wherein thestep of determining worst case bit patterns includes the step of:choosing a type of signal degradation parameter.
 20. The method asdefined in claim 19, wherein the step of choosing a type of signaldegradation parameter includes choosing a type of signal degradationfrom one of a low side signal degradation, a high side signaldegradation, a signal edge pull-in, and a signal edge push-off.
 21. Themethod as defined in claim 19, wherein the step of determining worstcase bit patterns also includes the step of: choosing an endingcondition.
 22. The method as defined in claim 21, wherein the step ofchoosing an ending condition includes choosing an ending condition fromone of a low output voltage level and a high output voltage level. 23.The method as defined in claim 21, wherein the step of determining worstcase bit patterns also includes the step of: analyzing one of a fallingedge vector generated based upon the first response and a rising edgevector generated based upon the second response to determine whether ornot a state transition will cause a desired signal degradation at theending condition.
 24. The method as defined in claim 23, wherein thestep of determining worst case bit patterns also includes the step of:analyzing one of the falling edge vector and the rising edge vector todetermine whether or not a state transition will cause a desired signaldegradation at each previously occurring bit time.
 25. The method asdefined in claim 24, wherein the step of determining worst case bitpatterns also includes the step of: repeating the step in claim 24 usinga desired amount of the falling edge vector and the rising edge vector.26. A computer signal embodied in a carrier wave readable by a computingsystem and encoding a computer program of instructions for executing acomputer process performing the method recited in claim
 1. 27. A signalembodied in a carrier wave and representing sequences of instructionswhich, when executed by at least one processor, cause the at least oneprocessor to determine performance characteristics of electronic systemsby performing the steps of: measuring a first response on a transmissionmedium from a falling edge transmitted on the transmission medium;measuring a second response on the transmission medium from a risingedge transmitted on the transmission medium; and determining worst casebit patterns for transmission on the transmission medium based upon thefirst response and the second response.
 28. An article of manufacturefor determining performance characteristics of electronic systems, thearticle of manufacture comprising: at least one processor readablecarrier; and instructions carried on the at least one carrier; whereinthe instructions are configured to be readable from the at least onecarrier by at least one processor and thereby cause the at least oneprocessor to operate so as to: measure a first response on atransmission medium from a falling edge transmitted on the transmissionmedium; measure a second response on the transmission medium from arising edge transmitted on the transmission medium; and determine worstcase bit patterns for transmission on the transmission medium based uponthe first response and the second response.
 29. An integrated circuitdevice having a transmitter for transmitting signals from the integratedcircuit device onto a transmission medium, the integrated circuit devicecomprising: a falling edge generator electrically connected to thetransmitter for generating a falling edge signal for transmission by thetransmitter onto the transmission medium so as to provide a falling edgeresponse associated with the transmission medium for generating anassociated falling edge vector; and a rising edge generator electricallyconnected to the transmitter for generating a rising edge signal fortransmission by the transmitter onto the transmission medium so as toprovide a rising edge response associated with the transmission mediumfor generating an associated rising edge vector.
 30. The integratedcircuit device as defined in claim 29, wherein the falling edgegenerator and the rising edge generator are formed in a combinedfalling/rising edge generator.
 31. An integrated circuit device having areceiver for receiving signals from a transmission medium, theintegrated circuit device comprising: a sampling and differencingcircuit electrically connected to the transmission medium for sampling asignal propagating along the transmission medium prior to being receivedby the receiver, and for calculating the difference between a sampledsignal value and a reference value.